The invention relates to an integrated circuit comprising a function section which generates logic data signals, a memory circuit fed therewith, and, connected to an output of the memory circuit, a logic output circuit for receiving an output signal from the memory circuit and transmitting this output signal, characterized in that the input and output of the memory circuit are separated, and in that the logic output circuit comprises a second input, connected in parallel to the input of the memory circuit while bypassing same, so as to bring the logic output circuit and the memory circuit direct into a logic state determined by a data signal originating from the function section, subsequent to which this logic output circuit is retained in this logic state by the output signal of the memory circuit.
A circuit of the general type mentioned above is known from IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October 1986: Flannagan et al., "Two 13-ns 64K CMOS SRAM's with very low active power and improved asynchronous circuit techniques", more specifically, FIG. 11. The memory circuit therein comprises a LATCH element having inputs and outputs connected to one another, and the logic output circuit comprises a plurality of inverting elements and three output transistors.
In the referenced paper the LATCH element is used for taking over the respective signals DATA and DATA during a logic-low control signal STABLE, so as to apply these signals with low output-impedances to the logic output circuit to diminish disturbing effects, for example caused by cross-talk from adjacent signal-conducting lines or caused by disturbances in the supplied power. Before new respective signals DATA and DATA are applied to the output buffer in a sequence of signals, input lines are latched to a logic-low level by means of transistors and a logic-high STABLE control signal, so that the LATCH element will not take over any faulty signal information and retain this information afterwards in the process of the development of the DATA and DATA signals as a function of time in a memory section not described in this paper. For this purpose, an exact tuning of the STABLE and CYC-END signals is required, because otherwise the LATCH element would be switched on at a logic-high STABLE control signal, as a result of which one of the input lines would be pulled up to a logic-high level. Such a situation causes undesirable dissipation. A greater certainty that the above will not occur is obtained by not allowing STABLE and CYC-END to overlap, but which will cause a delay. Thus, accurate tuning as a function of time is required between the STABLE monitoring signal and the CYC-END control signal. Owing to the blocking of the transistors M14, M15 and M16 during logic-low latched input lines for the duration of the signal transitions of the DATA and DATA signals at the beginning of a new read period (while CYC-END and STABLE are logic-high), the output DATA OUT is in a tri-state mode. With a supply voltage of approximately 5 volts, the voltage at the output of the logic output buffer will reach a value of approximately 1.7 volts when loaded by a Transistor-Transistor Logic (TTL) circuit (the load resistance to the first supply terminal being approximately twice as large as that to the second supply terminal) for the duration of the blocking state of the transistors M14, M15 and M16. This implies that the voltage at the output of the logic output buffer, with DATA and DATA signals remaining constant between the successive read periods, does not remain logic-high or logic-low, but is set to a level of approximately 1.7 volts despite the tri-state mode of the output buffer. These level variations are undesired since they form a source of possible cross-talk to any adjacent signal lines in an integrated circuit.